PC87427 datasheet(34/46 Pages) NSC

34 / 46 page

2.0 Device Characteristics (Continued)

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Revision 1.0

2.5.5

X-Bus Extension Timing

Symbol

Figure

Description

Reference Conditions

Min

Max

Unit

tVAL

Outputs

Output Valid Delay

After RE Internal Clock

CL =50pF

221

1. Not tested. Guaranteed by characterization.

tVAL_CS

Outputs

Output Valid Delay for

XCS3-0, XWR_XRW

After RE Internal Clock

CL =20pF

121

tVAL_XD

Outputs

Output Valid Delay for

XA19_XD15-XA4_XD0

After RE Internal Clock

CL =20pF

171

CL =50pF

201

tON

Outputs

Float to Active Delay

After RE Internal Clock

2. Not tested. Guaranteed by design.

tOH

Outputs

Output Hold time

After RE Internal Clock

tOFF

Outputs

Active to Float Delay

After RE Internal Clock

CL =50pF

301

tSU

Inputs

Input Setup Time

Before RE Internal Clock

tHL

Inputs

Input Hold Time

After RE Internal Clock

tCSDV

Mode 0, Speed

Grades 3, 4,

Read Transaction

Chip Select active to Data Valid

Read from External

Device

CL =20pF

CL =50pF

tSP4D

Mode 0, Speed

Grade 4, Write

Transaction

Chip Select active to

XWR_XRW active delay

Write to External Device CL =20pF

− 0.51 0.5

tON

Outputs

tVAL

tOFF

XSTB2-0, BIOS_SEL

(for reference only;

XA11-0, XRD_XEN,

Internal Clock

tOH

not available off chip)

tON

tVAL_CS

tOFF

XCS3-0, XWR_XRW

tOH

tON

tVAL_XD

tOFF

XA19_XD15-XA4_XD0

tOH

PC87427 Datasheet(PDF) 34 Page - National Semiconductor (TI)

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