PC87427 datasheet(36/46 Pages) NSC

36 / 46 page

2.0 Device Characteristics (Continued)

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Revision 1.0

2.5.6

SMBus Timing

Figure 12. SMBus Signals (SMBCLK and SMBDAT) Rising Time and Falling Time

Symbol

Figure

Description

Type of

Requirement1

1. An “Input” type is a value the PC87427 expects from the system; an “Output” type is a value the PC87427

provides to the system.

Min

Max

Unit

tSMBR

Rise time (SMBCLK and SMBDAT)

Input2

2. Test conditions: RL = 1 KΩ to VSB = 3.3V, CL = 400 pF to GND.

10003

3. Not tested. Guaranteed by design.

tSMBF

Fall time (SMBCLK and SMBDAT)

Input

3003

Output2

2504

4. Not tested. Guaranteed by characterization.

tSMBCKL

Clock low period (SMBCLK)

Input

4.7

µs

tSMBCKH

Clock high period (SMBCLK)

Input

µs

tSMBCY

Clock cycle (SMBCLK)

Input

µs

tSMBDS

Data setup time (before clock rising edge)

Input

250

Output2

250

tSMBDH

Data hold time (after clock falling edge)

Input

Output2

300

tSMBPS

Stop condition setup time (clock before data)

Input

µs

tSMBSH

Start condition hold time (clock after data)

Input

µs

tSMBBUF

Bus free time between Stop and Start

conditions (SMBDAT)

Input

4.7

µs

tSMBRS

Restart condition setup time (clock before

data)

Input

4.7

µs

tSMBRH

Restart condition hold time (clock after data)

Input

µs

tSMBLEX

Cumulative clock low extend time from Start

to Stop (SMBCLK)

Output

253

tSMBTO

Clock low time-out (SMBCLK)

Input

253,5

5. The PC87427 detects a time-out condition if SMBCLK is held low for more than tSMBTO.

Output

353,6

6. Upon detection of a time-out condition, the PC87427 resets the SMBus Interface no later than tSMBTO.

tSMBR

2.5V

0.4V

tSMBF

3.0V

0.4V

2.5V

0.4V

tSMBCKH

tSMBCKL

PC87427 Datasheet(PDF) 36 Page - National Semiconductor (TI)

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