PC87427 datasheet(17/46 Pages) NSC

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1.0 Signal/Pin Connection and Description (Continued)

Revision 1.0

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1.4.14 Testability

HFCKS

INTS

VSB

High Frequency Clock Selection. Sampled at VSB Power-Up

reset to determine the high frequency clock selection, as

follows:

For CKIN48=0:

No pull-down resistor:

40 MHz

10 K

Ω1 external pull-down resistor: 10 MHz

For CKIN48=1:

No pull-down resistor:

24 MHz

10 K

Ω1 external pull-down resistor: 6 MHz

XCNF2-0

91, 108,

IINTS

VSB

X-Bus Default Conﬁguration. Sampled at VSB Power-Up reset

to set the conﬁguration of the X-Bus transactions.

Pins

2 1 0 Functionality

1 1 x: No BIOS

1 0 1: 16-bit data BIOS, XSTB0 only

1 0 0: 16-bit data BIOS, XSTB0 and XSTB1

0 1 1: 8-bit data BIOS, XA11-4 multiplexed, XRDY disabled

0 1 0: 8-bit data BIOS, XA11-4 multiplexed, XRDY enabled

0 0 1: 8-bit data BIOS, XA11-4 direct, XRDY disabled

0 0 0: 8-bit data BIOS, XA11-4 direct, XRDY enabled

Pulled to 1 by internal resistor or set to 0 by external 10 K

Ω1 pull-

down resistor.

SMBSA

INTS

VSB

SMBus Slave Address. Sampled at VSB Power-Up reset to

determine the slave address of the device on SMBus, as follows

No pull-down resistor:

D8h, D9h

10 K

Ω external pull-down resistor: 60h, 61h

TEST

INTS

VDD

XOR Tree Test Mode. Sampled at VDD Power-Up reset to force

the device pins into a XOR tree conﬁguration.

No pull-down resistor (default):

Normal device operation

10 K

Ω1 external pull-down resistor: Pins configured as XOR tree.

When TEST is set to 0 (by an external pull-down resistor), TRIS

must be 1 (left unconnected).

CTEST

INTS

VSB

Complementary Test Mode. Sampled at VSB Power-Up reset

to set the device to Test Mode

No pull-down resistor:

Normal Operation mode

10 K

Ω external pull-down resistor: Test Mode

1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recom-

mended for Serial Port functionality; in this case, the value of the external pull-down resistor is 10 K

Ω. If, how-

ever, a TTL transceiver device is used, the value of the external pull-down resistor must be 470

Ω, and since the

Serial Port pins are not able to drive this load, the external pull-down resistor must be disconnected tIPLV after

VDD power-up (see “Reset Timing” on page 27).

Signal

Pin(s) I/O Buffer Type Power Well

Description

XOR_OUT

100

O4/8

VDD

XOR Tree Output. All the device pins (except power pins)

are internally connected in a XOR tree structure.

Signal

Pin(s)

I/O Buffer Type Power Well

Description

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