PC87427 datasheet(43/46 Pages) NSC

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2.0 Device Characteristics (Continued)

Revision 1.0

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Wake-Up Inputs at VDD Power Switching

Figure 18. Wake-Up Inputs at VDD Power Switching

Power Button Override

Figure 19. Power Button Override Timing

Symbol

Figure

Description

Reference Conditions

Min

Max

tEWIV

External Wake-up inputs

valid1

1. Not tested. Guaranteed by design.

After VDD power On

2. The 32 KHz clock domain is assumed to be toggling at VDD power stable.

24576 * t32KOSC

3. t32KOSC is the cycle time of the 32 KHz clock domain (see “Low Frequency Clock Timing” on page 31)

32768 * t32KOSC

Symbol

Figure

Description

Reference Conditions

Min

Max

tPBOV

Power Button Override1

1. Not tested. Guaranteed by design.

After PWBTIN active

3.89 s

3.92 s

tOVEX

Power Button Override

Extension1

After the end of tPBOV

0.2 s

0.24 s

tPBID

PWBTIN disable time1

After a Power-Off event

1 s

1.25 s

VDD (Power)

GPIOE10-17,

tEWIV

GPIOE40-47

VDDOFF

VDDON

(VDDLOAD=1)

tPBOV

PWBTIN

PWBTOUT

ONCTL

tOVEX

tPBID

PC87427 Datasheet(PDF) 43 Page - National Semiconductor (TI)

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