PC87427 datasheet(32/46 Pages) NSC

32 / 46 page

2.0 Device Characteristics (Continued)

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Revision 1.0

Figure 11. Internal Clock Waveforms

2.5.4

LPC Interface Timing

The AC characteristics of the LPC Interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V

DC signaling.

LCLK and LRESET

Symbol

Parameter

Min

Max

Units

tCYC

1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational parameters at

frequencies under 16 MHz are guaranteed by design rather than by testing. The clock frequency may be

changed at any time during the operation of the system as long as the clock edges remain “clean” (mono-

tonic) and the minimum cycle high and low times are not violated. The clock may only be stopped in a low

state.

LCLK Cycle Time

tHIGH

LCLK High Time2

2. Not tested. Guaranteed by characterization.

tLOW

LCLK Low Time2

LCLK Slew Rate2,3

3. Rise and fall times are speciﬁed in terms of the edge rate measured in V/ns. This slew rate must be met

across the minimum peak-to-peak portion of the clock wavering (0.2 VDD to 0.6 VDD) as shown below.

V/ns

LRESET Slew Rate2,4

4. The minimum LRESET slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures

that system noise cannot make an otherwise monotonic signal appear to bounce in the switching range.

mV/ns

VSB

t32KD

Internally Generated

40/48 MHz Clock

VBAT

CKVALID

(internal)

tHIGH

tLOW

tCYC

0.6 VDD

0.2 VDD

0.5 VDD

0.4 VDD

0.3 VDD

0.4 VDD p-to-p

(minimum)

VDD = 3.3V ±10%

PC87427 Datasheet(PDF) 32 Page - National Semiconductor (TI)

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