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PM6344 Datasheet(PDF) 177 Page - PMC-Sierra, Inc

Part # PM6344
Description  QUADRUPLE E1 FRAMER
PDF  256 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 177 Page - PMC-Sierra, Inc

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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
164
Register 046H, 0C6H, 146H, 1C6H: TRAN International/National Control
Bit
Type
Function
Default
Bit 7
R/W
Si[1]
1
Bit 6
R/W
Si[0]
1
Bit 5
Unused
X
Bit 4
R/W
Sn[4]
1
Bit 3
R/W
Sn[3]
1
Bit 2
R/W
Sn[2]
1
Bit 1
R/W
Sn[1]
1
Bit 0
R/W
Sn[0]
1
Sn[4:0]:
Bits 4 to 0 of this register are substituted in bit positions 4 to 8, respectively, of
TS0 of each NFAS frame when framing generation (FDIS = 0) and
International/National bit control (INDIS = 0) is enabled. When FDIS or INDIS
is logic 1, the contents of this register are ignored and replaced with the
values received on the BTPCM[x] input.
The bits Sn[4:0] correspond to the 5 National bits; these can be programmed
to any value and are inserted into the National bit positions in the NFAS
frames when enabled by INDIS.
Si[1:0]:
The bits Si[1] and Si[0] correspond to the International bits. The Si[1] and
Si[0] bits can be programmed to any value and will be inserted into bit 1 of
each FAS frame and NFAS frame, respectively, when the block is configured
for frame generation, INDIS is set to logic 0, and CRC multiframe generation
is disabled. When CRC multiframe generation is enabled, both Si[1] and Si[0]
are ignored if FEBE indication is enabled; if FEBEDIS is a logic 1 and INDIS =
0, the values programmed in the Si[1] and Si[0] bit positions are inserted into
the spare bit locations of frame 13 and frame 15, respectively, of the CRC
multiframe. If both FEBEDIS and INDIS are logic 1, then data from BTPCM[x]
replaces the Si[0] and Si[1] bits in the CRC multiframe.
The Si[1], Si[0], and Sn[4:0] bits should be programmed to a logic 1 when not
being used to carry information.



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