PM6344 datasheet(235/256 Pages) PMC

235 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

222

4. Microprocessor Interface timing applies to normal mode register accesses

only.

5. When a set-up time is specified between an input and a clock, the set-up time

is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt

point of the clock.

6. When a hold time is specified between an input and a clock, the hold time is

the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt

point of the input.

7. In non-multiplexed address/data bus architectures ALE should be held high

and parameters tSALR, tHALR, tVL, tSLR and tHLR are not applicable.

8. Parameter tHAR is not applicable when address latching is used.

9. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the

reference signal to ±300mV of the termination voltage on the output. The test

load is 50

Ω to 1.4V in parallel with 10 pf to GND.

Table 11

- Microprocessor Write Access (Figure 36)

Symbol

Parameter

Min

Max

Units

tSAW

Address to Valid Write Set-up

Time

tSDW

Data to Valid Write Set-up Time

tSALW

Address to Latch Set-up Time

tHALW

Address to Latch Hold Time

tVL

Valid Latch Pulse Width

tSLW

Latch to Write Set-up

tHLW

Latch to Write Hold

tHDW

Data to Valid Write Hold Time

tHAW

Address to Valid Write Hold Time

tVWR

Valid Write Pulse Width

PM6344 Datasheet(PDF) 235 Page - PMC-Sierra, Inc

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