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PM6344 Datasheet(PDF) 236 Page - PMC-Sierra, Inc |
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PM6344 Datasheet(HTML) 236 Page - PMC-Sierra, Inc |
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236 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 223 Figure 36 - Microprocessor Write Access Timing tH DW Valid Data D[7:0] tV WR tSAW tHAW tS DW (CSB+WRB) A[9:0] Valid Address ALE tVL tSALW tSLW tHALW tHLW Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. Microprocessor Interface timing applies to normal mode register accesses only. 3. In non-multiplexed address/data bus architectures, ALE should be held high and parameters tSALW, tHALW, tVL, tSLW and tHLW are not applicable. 4. Parameters tHAW and tSAW are not applicable if address latching is used. 5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. |
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