PM6344 datasheet(135/256 Pages) PMC

135 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

122

Bit

Type

Function

Default

Bit 7

OVR

Bit 6

NEWDATA

Bit 5

Unused

Bit 4

Unused

Bit 3

Unused

Bit 2

Unused

Bit 1

CRCE9

Bit 0

CRCE8

This register contains the most significant two bits of the 10-bit CRC error

counter value, updated every second.

NEWDATA:

The NEWDATA flag bit indicates that the counter register contents have been

updated with a new count value accumulated over the last 1 second interval.

It is set to logic 1 when the CRC error counter data is transferred into the

counter registers, and is reset to logic 0 when this register is read. This bit can

be polled to determine the 1 second timing boundary used by the FRMR.

OVR:

The OVR flag bit indicates that the counter register contents have not been

read within the last 1 second interval, and therefore have been over-written. It

is set to logic 1 if CRC error counter data is transferred into the counter

registers before the previous data has been read out, and is reset to logic 0

when this register is read.

This CRC error count is distinct from that of PMON because it is guaranteed to

be an accurate count of the number of CRC error in one second; whereas,

PMON relies on externally initiated transfers which may not be one second apart.

PM6344 Datasheet(PDF) 135 Page - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 135 Page - PMC-Sierra, Inc

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