PM6344 datasheet(132/256 Pages) PMC

132 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

119

Bit

Type

Function

Default

Bit 7

Si1

Bit 6

Si0

Bit 5

RAWRA

Bit 4

Sn0

Bit 3

Sn1

Bit 2

Sn2

Bit 1

Sn3

Bit 0

Sn4

Reading this register returns the current bit value of the International and

National bits collected over 2 consecutive frames. The Si1 bit position

corresponds to the value contained in the International bit position in the FAS

frame; the Si0, RAWRA, and Sn[4:0] bit positions correspond to the values

contained in the International, Remote Alarm Indication, and National bit

positions in the NFAS frame. This register is updated after time slot 0 of every

NFAS frame and the contents are valid for 2 frames (250µs). The contents of this

considered to constitute a byte value (i.e. the 5 national bits should not be

considered as indicating 1 of 32 possible values since it is possible that the

individual bits are not all from the same time instant due to the asynchronous

nature of the microprocessor reads). If the bits are to be interpreted as binary

values, care should be taken to ensure a coherent set of bit values by reading

the register at least twice.

The Si0, RAWRA and Sn0-Sn4 bits map to the TSO NFAS as follows:

Bit Position

Si0

RAWRA

Sn0

Sn1

Sn2

Sn3

Sn4

PM6344 Datasheet(PDF) 132 Page - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 132 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL