PM6344 datasheet(136/256 Pages) PMC

136 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

123

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

R/W

TS16AISE

Bit 5

TS16AISI

Bit 4

T16AIS

Bit 3

Unused

Bit 2

Unused

Bit 1

Unused

Bit 0

Unused

Reading this register returns the current value of the time slot 16 AIS status.

The TS16 AIS alarm algorithm accumulates the occurrences of TS16AISD (TS16

AIS detection) events. TS16AISD is defined as two consecutive all ones time slot

16 bytes while out of signaling multiframe. Each interval with a valid TS16 AIS

presence indication increments an interval counter which declares TS16 AIS

Alarm when 22 valid intervals have been accumulated. An interval with no valid

TS16 AIS presence indication decrements the interval counter; the TS16 AIS

Alarm declaration is removed when the counter reaches 0. This algorithm

provides a 99.1% probability of declaring an TS16 AIS Alarm within 3.1 ms after

loss of signaling multiframe detection in the presence of a 10-3 mean bit error

rate.

TS16AISE:

If the TS16AISE bit is a logic 1, an interrupt is generated when the TS16AIS

status bit changes state.

TS16AISI:

The TS16AISI bit is set high when the TS16AIS status bit changes state. It is

cleared when this register is read.

TS16AIS:

The TS16AIS bit is a logic one when an all ones condition has persisted in

time slot 16 for 3 ms. The bit returns to a logic zero when the time slot 16 AIS

condition has been absent for 3 ms.

PM6344 Datasheet(PDF) 136 Page - PMC-Sierra, Inc

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