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PM6344 Datasheet(PDF) 140 Page - PMC-Sierra, Inc |
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PM6344 Datasheet(HTML) 140 Page - PMC-Sierra, Inc |
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140 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 127 Register 033H, 0B3H, 133H, 1B3H: TPSC Block Timeslot Indirect Data Buffer Bit Type Function Default Bit 7 R/W D7 0 Bit 6 R/W D6 0 Bit 5 R/W D5 0 Bit 4 R/W D4 0 Bit 3 R/W D3 0 Bit 2 R/W D2 0 Bit 1 R/W D1 0 Bit 0 R/W D0 0 This register contains either the data to be written into the internal TPSC registers when a write request is initiated or the data read from the internal TPSC registers when a read request has completed. During normal operation, if data is to be written to the internal registers, the byte to be written must be written into this Data register before the target register's address and R/WB=0 is written into the Address/Control register, initiating the access. If data is to be read from the internal registers, only the target register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 480 ns, this register will contain the requested data byte. The internal TPSC registers control the per-timeslot functions on the Transmit PCM data, provide the per-timeslot Transmit IDLE Code, and provide the per- timeslot Transmit signaling control and the alternate signaling bits. The functions are allocated within the registers as follows: |
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