 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PM6344 Datasheet(PDF) 137 Page - PMC-Sierra, Inc |
|
|
|||||||||||||||||||||||||||||
PM6344 Datasheet(HTML) 137 Page - PMC-Sierra, Inc |
|
|
137 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 124 Register 030H, 0B0H, 130H, 1B0H: TPSC Block Configuration Bit Type Function Default Bit 7 Unused X Bit 6 Unused X Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 Unused X Bit 1 R/W IND 0 Bit 0 R/W PCCE 0 This register allows selection of the microprocessor read access type and output enable control for the Transmit Per-channel Serial Controller. IND: The IND bit controls the microprocessor access type: either indirect or direct. The IND bit must be set to logic 1 for proper operation. When the EQUAD is reset, the IND bit is set low, disabling the indirect access mode. PCCE: The PCCE bit enables the per-timeslot functions. When the PCCE bit is set to a logic 1, each timeslot's Data Control byte and IDLE Code byte are passed on to the TRAN block. When the PCCE bit is set to logic 0, the per- timeslot functions are disabled. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
