PM6344 datasheet(161/256 Pages) PMC

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PM6344 Datasheet(PDF) 161 Page - PMC-Sierra, Inc

161 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

148

Reserved:

The reserved bit must be programmed to logic 0 for proper operation.

IND:

The IND bit controls the microprocessor access type: either indirect or direct.

The IND bit must be set to logic 1 for proper operation. When the EQUAD is

reset, the IND bit is set low, disabling the indirect access mode.

PCCE:

The PCCE bit enables the per-timeslot functions. When the PCCE bit is set

to a logic 1, data inversion, trunk conditioning and signaling debouncing are

performed on a per-timeslot basis. When the PCCE bit is set to logic 0, the

per-timeslot functions are disabled.

Upon reset of the EQUAD, the ACCEL, MTKC, IND, and PCCE bits are all set to

logic 0 disabling µP indirect access and per-timeslot functions.

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