PM6344 datasheet(160/256 Pages) PMC

160 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

147

Bit

Type

Function

Default

Bit 7

R/W

ACCEL

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

R/W

MTKC

Bit 2

R/W

Reserved

Bit 1

R/W

IND

Bit 0

R/W

PCCE

This register allows selection of the microprocessor access type, and allows

enabling of the per-timeslot configuration registers.

ACCEL:

The ACCEL bit is used to enable an accelerated test mode for production

purposes only. For proper operation the ACCEL bit must be set to logic 0.

MTKC:

The master trunk conditioning bit, MTKC, enables trunk conditioning for all

timeslots, regardless of per-timeslot settings. A logic 1 in the MTKC bit

position enables master trunk conditioning. Data from all of the timeslot Trunk

Conditioning Data registers (40H to 5FH) is output onto the data stream

BRPCM and the per-timeslot signaling trunk conditioning bits A’,B’,C’ and D’

are output onto the signaling data stream BRSIG. The MTKC bit is ORed

with the per-timeslot trunk conditioning enable bits in the Per-Timeslot

Configuration Registers to form the applied per-timeslot trunk conditioning

enables. When the EQUAD is reset, the MTKC bit is set to logic 0, disabling

master trunk conditioning.

The MTKC bit is independent of the TRKEN bit of the EQUAD Receive

Options register and takes precedence over it. If TRKEN is a logic 1, an out-

of-frame condition causes the contents of the ELST Idle Code register to

placed in all time slots on BRPCM. BRSIG presents the frozen signaling. If

MTKC is a logic 1, each BRPCM and BRSIG time slot may have an unique

idle code.

PM6344 Datasheet(PDF) 160 Page - PMC-Sierra, Inc

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