PM6344 datasheet(156/256 Pages) PMC

156 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

143

Registers 03CH, 0BCH, 13CH and 1BCH: Interrupt ID/Clock Monitor

Bit

Type

Function

Default

Bit 7

INT4

Bit 6

INT3

Bit 5

INT2

Bit 4

INT1

Bit 3

BTCLKA

Bit 2

TCLKIA

Bit 1

BRCLKA

Bit 0

RCLKIA

These registers provide interrupt identification and activity monitoring on EQUAD

clocks. The framer which caused the INTB output to transition low can be

identified by reading register 03CH - the INTx bits in register 0BCH, 13CH, and

1BCH are invalid. The INTx bit in register 03CH will be high if the xth framer

caused the interrupt. The Interrupt Source registers of that framer can then be

used to find which block within the framer generated the interrupt.

When a monitored clock signal makes a low to high transition, the corresponding

point, all the bits in this register are cleared. A lack of transitions is indicated by

the corresponding register bit reading low. These registers should be read at

periodic intervals to detect clock failures.

INT4, INT3, INT2, INT1:

The INTx bit will be high if the xth framer (the framer corresponding to the

input pin BTCLK[x]) caused the INTB pin to transition low.

BTCLKA:

The BTCLK active (BTCLKA) bit monitors for low to high transitions on the

BTCLK[x] input. BTCLKA is set high on a rising edge of BTCLK[x], and is set

low when this register is read.

TCLKIA:

The TCLKI active (TCLKIA) bit monitors for low to high transitions on the

TCLKI[x] input. TCLKIA is set high on a rising edge of TCLKI[x], and is set

low when this register is read.

PM6344 Datasheet(PDF) 156 Page - PMC-Sierra, Inc

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