PM6344 datasheet(152/256 Pages) PMC

152 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

139

Bit

Type

Function

Default

Bit 7

Bit 6

OVR

Bit 5

FLG

Bit 4

EOM

Bit 3

CRC

Bit 2

NVB2

Bit 1

NVB1

Bit 0

NVB0

The FLG and EOM bits in this register contain values which correspond to the

last byte read from the RFDL Data Register.

FE:

The FIFO Empty bit (FE) is high when the last FIFO entry is read and goes

low when the FIFO is loaded with new data.

OVR:

The Receiver Overrun bit (OVR) is set when data is written over unread data

in the FIFO. This bit is not reset until after the RFDL Status register is read.

While OVR is high, the RFDL and FIFO are held in the reset state, causing

the FLG and EOM bits in the status register to be reset also.

FLG:

The flag bit (FLG) is set if the RFDL has detected the presence of the LAPD

flag sequence (01111110) in the data. FLG is reset only when the LAPD

abort sequence (01111111) is detected in the data or when the RFDL is

disabled. This bit is passed through the FIFO with the Data so that the status

of this bit will correspond to the data just read from the RFDL Data Register.

The reception of bit-oriented codes over the data link will also force an abort

due to its eight ones pattern.

EOM:

The End of Message bit (EOM) follows the RDLEOM[x] output. It is set

when:

PM6344 Datasheet(PDF) 152 Page - PMC-Sierra, Inc

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