PM6344 datasheet(150/256 Pages) PMC

150 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

137

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

Unused

Bit 2

R/W

INTC1

Bit 1

R/W

INTC0

Bit 0

INT

INTC1,INTC0:

The INTC1 and INTC0 bits control when an interrupt is asserted based on the

number of received data bytes in the FIFO as follows:

INTC1

INTC0

Description

Disable interrupts (All sources)

Enable interrupt when FIFO receives data

Enable interrupt when FIFO has 2 bytes of

data

Enable interrupt when FIFO has 3 bytes of

data

INT:

The INT bit reflects the status of the external RDLINT[x] interrupt unless the

INTC1 and INTC0 bits are set to disable interrupts. In that case, the

RDLINT[x] output is forced to 0 and the INT bit of this register will reflect the

state of the internal interrupt latch.

In addition to the FIFO fill status, interrupts are also generated for EOM (end of

message), OVR (FIFO overrun), detection of the abort sequence while not

receiving all ones and on detection of the first flag while receiving all ones. The

interrupt is reset by a RFDL Receive Data Register read that empties the FIFO,

unless the cause of the interrupt was due to a FIFO overrun. The interrupt due to

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