PM6344 datasheet(147/256 Pages) PMC

147 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

134

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

Unused

Bit 2

Unused

Bit 1

INT

Bit 0

R/W

UDR

INT:

The INT bit indicates when the XFDL block is ready to accept a new data byte

for transmission. The INT bit is set to a logic 1 when the previous byte in the

Transmit Data register has been loaded into the parallel to serial converter

and a new byte can be written into the XFDL Transmit Data register. The INT

bit is set to a logic 0 while new data is in the Transmit Data register. The INT

bit is not disabled by the INTE bit in the configuration register.

UDR:

The UDR bit indicates when the XFDL block has underrun the data in the

XFDL Transmit Data register. The UDR bit is set to a logic 1 if the parallel to

serial conversion of the last byte in the XFDL Transmit Data register has

completed before the new byte was written into the XFDL Transmit Data

followed by a flag, and waits to transmit the next valid data byte. If the UDR bit

is still set after the transmission of the flag the XFDL will continuously transmit

the all-ones idle pattern. The UDR bit can only be cleared by writing a logic 0

to the UDR bit position in this register.

PM6344 Datasheet(PDF) 147 Page - PMC-Sierra, Inc

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