PM6344 datasheet(145/256 Pages) PMC

145 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

132

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

R/W

EOM

Bit 3

R/W

INTE

Bit 2

R/W

ABT

Bit 1

R/W

CRC

Bit 0

R/W

EOM:

The EOM bit indicates that the last byte of data written in the XFDL Transmit

Data register is the end of the present data packet. If the CRC bit is set then

the 16-bit FCS word is appended to the last data byte transmitted and a

continuous stream of flags is generated. The EOM bit is automatically cleared

before transmission of the next data packet begins.

INTE:

The INTE bit enables the generation of an interrupt via the TDLINT[x] output.

Setting the INTE bit to logic 1 enables the generation of an interrupt; setting

INTE to logic 0 disables the generation of an interrupt. If the TDLINTE bit is

also set to logic 1 in the Datalink Options register, the interrupt generated on

the TDLINT[x] output is also generated on the microprocessor INTB pin.

ABT:

The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC

abort code. Setting the ABT bit to a logic 1 causes the 11111110 code to be

transmitted after the last byte from the XFDL Transmit Data Register is

transmitted. Aborts are continuously sent until this bit is reset to a logic 0.

CRC:

The CRC enable bit controls the generation of the ITU-T-CRC frame check

sequence (FCS). Setting the CRC bit to logic 1 enables the ITU-T-CRC

generator and the appends the 16 bit FCS to the end of each message.

When the CRC bit is set to logic 0, the FCS is not appended to the end of the

PM6344 Datasheet(PDF) 145 Page - PMC-Sierra, Inc

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