PM6344 datasheet(149/256 Pages) PMC

149 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

136

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

Unused

Bit 2

Unused

Bit 1

R/W

Bit 0

R/W

TR:

Setting the terminate reception bit (TR) forces the RFDL block to immediately

terminate the reception of the current LAPD frame, empty the FIFO, clear the

interrupts, and begin searching for a new flag sequence. The RFDL handles

the TR input in the same manner as if the EN bit had been cleared and then

set. The TR bit in the Configuration register will reset itself after a rising and

falling edge have occurred on the CLK input to the RFDL block once the write

to this register has completed and WRB goes inactive. If the Configuration

EN:

The enable bit (EN) controls the overall operation of the RFDL block. When

set, the RDFL block is enabled; when reset the RFDL block is disabled.

When the block is disabled, the FIFO and interrupts are all cleared, however,

the programming of the RFDL Interrupt Control/Status register is not affected.

When the block is enabled, it will immediately begin looking for flags.

The RFDL block handles the TR input in the same manner as clearing and

setting the EN bit, therefore, the RFDL state machine will begin searching for

flags and an interrupt will be generated when the first flag is detected.

PM6344 Datasheet(PDF) 149 Page - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 149 Page - PMC-Sierra, Inc

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