PM6344 datasheet(153/256 Pages) PMC

153 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

140

1) The last byte in the LAPD frame (EOM) is being read from the Receive

Data Register,

2) An abort sequence is detected while not in the receiving all-ones state

and the byte, written to the FIFO due to the detection of the abort sequence,

is being read from the FIFO,

3) The first flag has been detected and the dummy byte, written into the

FIFO when the RFDL changes from the receiving all-ones state to the

receiving flags state, is being read from the FIFO,

4) Immediately on detection of FIFO overrun.

The EOM bit is passed through the FIFO with the Data so that the status of

this bit will correspond to the data just read from the RFDL Data Register.

CRC:

The CRC bit is set if a CRC error was detected in the last received HDLC

frame. The CRC bit is only valid when EOM is logic 1 and FLG is a logic 1

and OVR is a logic 0.

NVB[2:0]:

The NVB[2:0] bit positions indicate the number of valid bits in the RFDL

Receive Data Register byte. It is possible that not all of the bits in the RFDL

Receive Data Register are valid when the last data byte is read since the data

frame can be any number of bits in length and not necessarily an integral

number of bytes. The RFDL Receive Data Register is filled starting from the

MSB bit position (RD7) and the data bits are shifted to lower bit positions as

more bits are received, with one to eight data bits being valid. The number of

valid bits is equal to 1 plus the value of NVB[2:0]. An NVB[2:0] value of 000

binary indicates that only the FE bit in this register is valid. An NVB[2:0] value

of 011 indicates that RD[7:4] contain valid data bits where RD4 is the data bit

that was received first. NVB[2:0] is only valid when the EOM bit is a logic 1

and the FLG bit is a logic 1 and the OVR bit is a logic 0.

On an interrupt generated from the detection of the first flag, reading the RFDL

Status register will return invalid NVB[2:0] and CRC bits, even though the EOM

bit is logic 1 and the FLG bit is logic 1.

If the Receive Data register is read while there is no valid data, then a FIFO

underrun condition occurs. The underrun condition is reflected in the Status

PM6344 Datasheet(PDF) 153 Page - PMC-Sierra, Inc