PM6344 datasheet(155/256 Pages) PMC

155 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

142

Bit

Type

Function

Default

Bit 7

RD7

Bit 6

RD6

Bit 5

RD5

Bit 4

RD4

Bit 3

RD3

Bit 2

RD2

Bit 1

RD1

Bit 0

RD0

The RFDL Receive Data Register is filled starting from the MSB bit position

(RD7) and the data bits are shifted to lower bit positions as more bits are

received, with one to eight data bits being valid. The number of valid bits is equal

to 1 plus the value of NVB[2:0] from the RFDL Status Register. An NVB[2:0]

value of 111 indicates that RD[7:0] contain valid data bits where RD0

corresponds to the first bit of the serial byte received by the RFDL.

These registers are actually 4 level FIFOs. If data is available, the FE bit in the

RFDL Status register is low. If INTC[1:0] (in the RFDL Interrupt Control/Status

prevent an overrun. If INTC[1:0] is set to 11, this register must be read within 15

data bit periods.

When an overrun is detected, an interrupt is generated and the FIFO is held

cleared until the Status register is read. When the LAPD abort sequence

(01111111) is detected in the data an ABORT interrupt is generated and the

data that has been shifted into the serial to parallel converter is written into the

FIFO.

A read of this register increments the FIFO pointer at the end of the read. If this

incrementing. The underrun condition will be signaled in the next RFDL Status

PM6344 Datasheet(PDF) 155 Page - PMC-Sierra, Inc

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