S124 datasheet(59/98 Pages) RENESAS

59 / 98 page

R01DS0264EU0100 Rev.1.00

Page 59 of 95

Feb 23, 2016

S124

2. Electrical Characteristics

Note 1. tPcyc: PCLKB cycle.

Note 2. N is set as an integer from 1 to 8 by the SPCKD register.

Note 3. N is set as an integer from 1 to 8 by the SSLND register.

SPI

Data output delay

Master

2.7V or above

tOD

Figure 2.43 to

Figure 2.48

C = 30PF

2.4V or above

1.8V or above

1.6V or above

Slave

2.7V or above

2.4V or above

1.8V or above

1.6V or above

110

Data output hold

time

Master

tOH

Slave

Successive

transmission delay

Master

tTD

tSPcyc + 2 ×

tPcyc

8 × tSPcyc

+ 2 × tPcyc

Slave

6 × tPcyc

MOSI and MISO

rise and fall time

Output

2.7V or above

tDr, tDf

2.4V or above

1.8V or above

1.6V or above

Input

1µs

SSL rise and fall

time

Output

2.7V or above

tSSLr, tSSLf

2.4V or above

1.8V or above

1.6V or above

Input

µs

Slave access time

2.7V or above

tSA

2 × tPcyc +50

Figure 2.47 and

Figure 2.48

C = 30PF

2.4V or above

2 × tPcyc +60

1.8V or above

2 × tPcyc +85

1.6V or above

2 × tPcyc +110

Slave output release time

2.7V or above

tREL

2 × tPcyc +50

2.4V or above

2 × tPcyc +60

1.8V or above

2 × tPcyc +85

1.6V or above

2 × tPcyc +110

Table 2.35

SPI timing (2/2)

Conditions: Middle drive output is selected in the Drive Strength Control bit in the PmnPFS register.

Item

Symbol

Min

Max

Unit*1

Test conditions

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