S124 datasheet(3/98 Pages) RENESAS

3 / 98 page

R01DS0264EU0100 Rev.1.00

Page 3 of 95

Feb 23, 2016

S124

1. Overview

Low Voltage Detection (LVD)

The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin and the

detection level can be selected using a software program. See section 7, Low Voltage

Detection (LVD) in User's Manual.

Clock

 Main clock oscillator (MOSC)

 Sub-clock oscillator (SOSC)

 High-speed on-chip oscillator (HOCO)

 Middle-speed on-chip oscillator (MOCO)

 Low-speed on-chip oscillator (LOCO)

 Independent Watchdog Timer on-chip oscillator

 Clock out support.

See section 8, Clock Generation Circuit in User's Manual.

Clock Frequency Accuracy

Measurement Circuit (CAC)

The clock frequency accuracy measurement circuit (CAC) is used to check the system clock

frequency with a reference clock signal by counting the number of pulses of the system clock

to be measured. The reference clock can be provided externally through a CACREF pin or

internally from various on-chip oscillators.

Event signals can be generated when the clock does not match or measurement ends.

This feature is particularly useful in implementing a fail-safe mechanism for home and

industrial automation applications.

See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User's Manual.

Low Power Mode

The MCU has several functions for reducing power consumption, such as setting clock

dividers, stopping modules, selecting power control mode in normal operation, and

transitioning to low power modes. See section 10, Low Power Modes in User's Manual.

The Register Write Protection function protects important registers from being overwritten due

to software errors. See section 11, Register Write Protection in User's Manual.

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The

refresh-permitted period can be set to refresh the counter and used as the condition to detect

when the system runs out of control. See section 22, Watchdog Timer (WDT) in User's Manual.

Independent Watchdog Timer (IWDT)

The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset

the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the

timer operates with an independent, dedicated clock source, it is particularly useful in returning

the MCU to a known state as a fail safe mechanism when the system runs out of control. The

watchdog timer can be triggered automatically on reset, underflow, or refresh error, or by a

refresh of the count value in the registers. See section 23, Independent Watchdog Timer

(IWDT) in User's Manual.

Table 1.4

Interrupt Control

Feature

Functional description

Interrupt Controller Unit (ICU)

The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC

module. The ICU also controls NMI interrupts. See section 12, Interrupt Controller Unit (ICU) in

User's Manual.

Table 1.5

Event Link

Feature

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral

modules as event signals to connect them to different modules, enabling direct interaction

between the modules without CPU intervention. See section 15, Event Link Controller (ELC) in

User's Manual.

Table 1.6

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

The MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when

activated by an interrupt request. See section 14, Data Transfer Controller (DTC) in User's

Manual.

Table 1.3

System (2/2)

Feature

Functional description

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