XRT4500CV datasheet(43/99 Pages) EXAR

43 / 99 page

XRT4500

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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

REV. 1.0.7

1.2.1

The “High -Speed Transceiver” Block

The “High-Speed Transceiver” block supports the

transmission and reception of high speed data and

clock signals for the selected “Communication Inter-

face”. This block contains receivers RX1 and RX2,

transmitters TX1 and TX2, and bi-directional trans-

ceiver TR3 which is composed of TX3 and RX3. Each

of these devices may be configured to support the

“Electrical Interface” requirements per ITU-T V.35,

ITU-T V.11 (EIA-422), ITU-T V.10 (EIA-423), or ITU-T

V.28 (EIA-232). In the “ITU-T V.35” Mode, each trans-

mitter has a common mode pin that is connected to

the center of the internal termination. This pin should

be bypassed to ground with an external 0.1µF capac-

itor in order to provide the best possible driver output

stage balance.

In a system application, the TX1-RX1 pair and TX2-RX2

pair handle the TXD-RXD (Transmit Data - Receive

Data) and the TXC-RXC (Transmit Clock - Receive

Clock) high speed interface signals respectively. Trans-

ceiver TR3 is dedicated to the SCTE (Transmit Clock

Echo) signal for both DCE and DTE modes of operation.

Transceiver TR3 functions as a receiver for the DTE

mode and as a transmitter during the DCE mode.

FIGURE 12. HIGH-SPEED TRANSCEIVER BLOCK

XRT4500CV Datasheet(PDF) 43 Page - Exar Corporation