LTC5100 datasheet(48/52 Pages) LINER

48 / 52 page

LTC5100

sn5100 5100fs

APPLICATIO S I FOR ATIO

The termination resistor, R1, and its decoupling capacitor,

C1, are placed as close as possible to the LTC5100 to

reduce inductance. Inductance in these two components

causes high frequency peaking and overshoot in the

current delivered to the laser. R1 and C1 are folded against

each other so that their mutual inductance and counter-

flowing current partially cancel their self-inductance. C1

has two vias to the ground plane and a trace directly to Pin

12. The layout shows the EEPROM placed next to the

LTC5100. However, placement of the EEPROM is not

critical. It can be placed several centimeters from the

LTC5100 or on the back of the PC board if desired.

The transmission line connecting the MODB pin to the

laser has a short length of minimum width trace. The net

inductance of this section of trace helps compensate on-

chip capacitance to further reduce reflections from the

chip.

FAULT

SDA

SCL VDD(HS)

VDD

VSS

IN+

IN–

VSS

MODA

MODB

VSS

SRC

LTC5100

Ω

10nF

ZO = 50Ω

FERRITE

BEAD

ENABLE

+TX_DATA

–TX_DATA

FAULT

VDD + 3.3V

VSS

FIBER

10nF

24LC00

EEPROM

SOT23 PACKAGE

PROGRAMMING

PADS

5100 F29

ZO = 50Ω

10nF

VCC

SCL

VSS

SDA

IN+

VSS

IN–

EEPROM

VSS

5100 F32

MODA

MODB

VSS 4

5678

SCL

VCC

VSS

SDA

Figure 31. Schematic of a Minimum Output Reflection Coefficient Circuit

Figure 32. Layout of the Minimum Reflection Coeffieicnt Circuit Using 0402 Passive Components

LTC5100 Datasheet(PDF) 48 Page - Linear Technology

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