IPAC-X datasheet(31/270 Pages) INFINEON

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IPAC-X

PSB/PSF 21150

Pin Configuration

Data Sheet

2003-01-30

MODE1

EAW

The pin function depends on the setting of MODE0.

If MODE0=1: Mode 1 Select

A LOW selects LT-T mode and a HIGH selects LT-

S mode.

If MODE0=0: External Awake

If a falling edge on this input is detected, the IPAC-

X generates an interrupt and, if enabled, a reset

pulse.

ACL

Activation LED

This pin can either function as a programmable

output or it can automatically indicate the activated

state of the S interface by a logic ’0’.

An LED with pre-resistance may directly be

connected to ACL.

C768

Clock Output

A 7.68 MHz clock is output to support other devices.

This clock is not synchronous to the S interface.

6RSTO

Reset Output

Low active reset output, either from a watchdog

timeout or programmed by the host.

4TP

Test Pin

Must be connected to

SS.

2, 42

n.c.

not connected

Power Supply

8, 18, 33,

–

Digital Power Supply Voltage

(3.3 V

± 5%)

DDA

–

Analog Power Supply Voltage

(3.3 V

± 5%)

Table 2

IPAC-X Pin Definitions and Functions (cont’d)

Pin No.

MQFP-64

TQFP-64

Symbol Input (I)

Output (O)

Open Drain

(OD)

Function

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