IPAC-X datasheet(44/270 Pages) INFINEON

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IPAC-X

PSB/PSF 21150

Description of Functional Blocks

Data Sheet

2003-01-30

• C/I Code Change (Exchange Awake)

A change in the downstream C/I channel (C/I0) generates an external reset pulse of

125 µs

£ t £ 250 µs.

• EAW (Subscriber Awake)

A low level on the EAW input starts the oscillator from the power down state and

generates a reset pulse of 125 µs

£ t £ 250 µs.

• Watchdog Timer

After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and

started. During every time period of 128 ms the microcontroller has to program the

WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:

If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse

of 125 µs is generated.

Deactivation of the watchdog timer is only possible with a hardware reset.

External Reset Input

At the RES input an external reset can be applied forcing the device in the reset state.

This external reset signal is additionally fed to the RSTO output. The length of the reset

signal is specified in Chapter 5.9.

After an external reset from the RES pin all registers of the device are set to its reset

values (see register description in Chapter 4).

Software Reset Register (SRES)

Every main functional block of the device can be reset separately by software setting the

corresponding bit in the SRES register. A reset to external devices can also be controlled

in this way. The reset state is activated by setting the corresponding bit to ’1’ and onchip

Table 6

Reset Source Selection

RSS2

Bit 1

RSS1

Bit 0

C/I Code

Change

EAW

Watchdog

Timer

reserved

WTC1

WTC2

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