IPAC-X datasheet(13/270 Pages) INFINEON

13 / 270 page

IPAC-X

PSB/PSF 21150

Overview

Data Sheet

2003-01-30

1Overview

The ISDN PC Adapter Circuit Extended IPAC-X integrates all necessary functions for a

host based ISDN access solution on a single chip. It is based on the IPAC PSB 2115,

and provides enhanced features and functionality.

It includes the S-transceiver (Layer 1), an HDLC controller for the D-channel and two

protocol controllers for each B-channel. They can be used for HDLC protocol or

transparent access.

The system integration is simplified by several configurations of the parallel

microcontroller interface selected via pin strapping. They include multiplexed and

demultiplexed interface selection as well as the optional indirect register access

mechanism which reduces the number of necessary registers in the address space to 2

locations. The IPAC-X also provides a serial control interface (SCI).

The FIFO size of the cyclic B-channel buffers is 128 bytes per channel and per direction,

with programmable block size (threshold). Besides TE mode the S-transceiver supports

other terminal relevant operation modes like line termination subscriber side (LT-S) and

line termination trunk side (LT-T). A multi-line ISDN solution to support both S and U line

coding is simplified as well as multi-line solution with up to 3 S-interfaces.

An auxiliary I/O port has been added with interrupt capabilities on two input lines. These

programmable I/O lines may be used to connect peripheral components to the IPAC-X

which need software control or have to forward status information to the host.

Three programmable LED outputs can be used to indicate certain status information,

one of them is capable to indicate the activation status of the S-interface automatically.

The IPAC-X is produced in advanced CMOS technology.

IPAC-X Datasheet(PDF) 13 Page - Infineon Technologies AG