IPAC-X datasheet(9/270 Pages) INFINEON

9 / 270 page

IPAC-X

PSB/PSF 21150

List of Figures

Page

Data Sheet

2003-01-30

Figure 1

Logic Symbol of the IPAC-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2

ISDN PC Adapter Card for S Interface . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 3

ISDN PC Adapter Card for U or S Interface. . . . . . . . . . . . . . . . . . . . . 21

Figure 4

ISDN Voice/Data Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 5

ISDN Stand-Alone Terminal with POTS Interface . . . . . . . . . . . . . . . . 23

Figure 6

Pin Configuration of the IPAC-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7

Functional Block Diagram of the IPAC-X . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 8

Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9

Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 10

Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 11

Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12

Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 13

Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 14

Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 15

Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 16

ACL Indication of Activated Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 17

ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 18

Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 19

S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 20

Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 51

Figure 21

Multiframe Synchronization using the M-Bit. . . . . . . . . . . . . . . . . . . . . 54

Figure 22

Sampling Time in LT-S / NT Mode (M-Bit input) . . . . . . . . . . . . . . . . . 55

Figure 23

Frame Relationship in LT-S / NT Mode (M-Bit input) . . . . . . . . . . . . . . 55

Figure 24

Frame Relationship in TE / LT-T Mode (M-Bit output) . . . . . . . . . . . . . 56

Figure 25

Data Delay Between IOM-2 and S/T Interface Transparent Mode

(TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 26

Data Delay Between IOM-2 and S/T Interface With S/G Bit Evaluation

(TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 27

Data Delay Between IOM-2 and S/T Interface With 8 IOM Channels

(LT-S/NT mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 28

Data Delay Between IOM-2 and S/T Interface With 3 IOM Channels

a Maximum Receive Delay(LT-S/NT mode only). . . . . . . . . . . . . . . . . 59

Figure 29

Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . . 60

Figure 30

Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . . 61

Figure 31

Connection of Line Transformers and Power Supply to the IPAC-X . . 62

Figure 32

External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 33

External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 64

Figure 34

External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 65

Figure 35

Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 36

External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 37

Clock System of the IPAC-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 38

Phase Relationships of IPAC-X Clock Signals . . . . . . . . . . . . . . . . . . 71

IPAC-X Datasheet(PDF) 9 Page - Infineon Technologies AG

IPAC-X Datasheet(HTML) 9 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL