IPAC-X datasheet(71/270 Pages) INFINEON

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IPAC-X

PSB/PSF 21150

Description of Functional Blocks

Data Sheet

2003-01-30

3.4.1

Description of the Receive PLL (DPLL)

The receive PLL performs phase tracking between the F/L transition of the receive signal

and the recovered clock. Phase adjustment is done by adding or subtracting 0.5 or 1

XTAL period to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to

generate any other clock synchronized to the line.

During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to

have high or low times as short as 130 ns. After the S/T interface frame has achieved

the synchronized state (after three consecutive valid pairs of code violations) the FSC

output in TE mode is set to a specific phase relationship, thus causing once an irregular

FSC timing.

The phase relationships of the clocks are shown in Figure 38.

Figure 38

Phase Relationships of IPAC-X Clock Signals

3.4.2

Jitter

The timing extraction jitter of the IPAC-X conforms to ITU-T Recommendation I.430

(– 7% to + 7% of the S-interface bit period).

ITD09664

7.68 MHz

1536 kHz *

768 kHz

* Synchronous to receive S/T. Duty Ratio 1:1 Normally

F-bit

FSC

IPAC-X Datasheet(PDF) 71 Page - Infineon Technologies AG