IPAC-X datasheet(33/270 Pages) INFINEON

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IPAC-X

PSB/PSF 21150

Description of Functional Blocks

Data Sheet

2003-01-30

Description of Functional Blocks

3.1

General Functions and Device Architecture

Figure 7 shows the architecture of the IPAC-X containing the following functions:

• S/T-interface transceiver

• Serial or parallel microcontroller interface

• Two B-channel HDLC-controller with 128 byte FlFOs per channel and per direction

with programmable FIFO block size (threshold)

• One D-channel HDLC-controller with 64 byte FlFOs per direction with programmable

FIFO block size (threshold)

• IOM-2 interface for terminal (TE mode), linecard (LT-T or LT-S) or NT applications

• D-channel access mechanism in all modes

• D-channel priority handler on IOM-2 for intelligent NT applications

• C/I- and Monitor channel handler

• Auxiliary interface with interrupt and general purpose I/O lines and LED drivers

• Clock and timing generation

• Digital PLL to synchronize the transceiver to the S/T interface

• Reset generation (watchdog timer)

The functional blocks are described in the following chapters.

Figure 7

Functional Block Diagram of the IPAC-X

Reset

Interrupt

-generation

SCI

8-bit parallel

IOM-2 Interface

IOM-2 Handler

B-channel

HDLC

RX/TX

FIFOs

B-channel

HDLC

RX/TX

FIFOs

D-channel

HDLC

RX/TX

FIFOs

Auxiliary

Interface

S Transceiver

C/I

TIC

MON

Handler

Host Interface

OSC

DPLL

Host

Peripheral Devices

I/O- and

Interrupt

Lines

21150_18

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