CS5530A datasheet(189/259 Pages) AMD

189 / 259 page

AMD Geode™ CS5530A Companion Device Data Book

189

Revision 1.1

Table 5-21. F3BAR+Memory Offset xxh: XpressAUDIO™ Subsystem Configuration Registers

Bit

Description

Offset 00h-03h

Codec GPIO Status Register (R/W)

Reset Value = 00100000h

Codec GPIO Interface: 0 = Disable; 1 = Enable.

Codec GPIO SMI: Allow codec GPIO interrupt to generate an SMI. 0 = Disable; 1= Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1].

Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[1].

29:21

Reserved: Set to 0.

Codec GPIO Status Valid (Read Only): Is the status read valid? 0 = Yes; 1 = No.

19:0

Codec GPIO Pin Status (Read Only): This is the GPIO pin status that is received from the codec in slot 12 on SDATA_IN

signal.

Offset 04h-07h

Codec GPIO Control Register (R/W)

Reset Value = 00000000h

31:20

Reserved: Set to 0.

19:0

Codec GPIO Pin Data: This is the GPIO pin data that is sent to the codec in slot 12 on the SDATA_OUT signal.

Offset 08h-0Bh

Codec Status Register (R/W)

Reset Value = 00000000h

31:24

Codec Status Address (Read Only): Address of the register for which status is being returned. This address comes from

slot 1 bits [19:12].

Codec Serial INT SMI: Allow codec serial interrupt to generate an SMI. 0 = Disable; 1= Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[1].

Second level SMI status is reported at F3BAR+Memory Offset 10h/12h[1].

SYNC Pin: Selects SYNC pin level. 0 = Low; 1 = High.

Enable SDATA_IN2: Pin AE24 function selection. 0 = GPIO1; 1 = SDATA_IN2.

For this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0).

Audio Bus Master 5 AC97 Slot Select: Selects slot for Audio Bus Master 5 to receive data. 0 = Slot 6; 1 = Slot 11.

Audio Bus Master 4 AC97 Slot Select: Selects slot for Audio Bus Master 4 to transmit data. 0 = Slot 6; 1 = Slot 11.

Reserved: Set to 0.

Status Tag (Read Only): Determines if the status in bits [15:0] is new or not. 0 = Not new; 1 = New.

Codec Status Valid (Read Only): Is the status in bits [15:0] valid? 0 = No; 1 = Yes.

15:0

Codec Status (Read Only): This is the codec status data that is received from the codec in slot 2 on SDATA_IN. Only bits

[19:4] are used from slot 2.

Offset 0Ch-0Fh

Codec Command Register (R/W)

Reset Value = 00000000h

31:24

Codec Command Address: Address of the codec control register for which the command is being sent. This address goes

in slot 1 bits [19:12] on SDATA_OUT.

23:22

CS5530A Codec Communication: Selects which codec to communicate with.

00 = Primary codec

10 = Third codec

01 = Secondary codec

11 = Fourth codec

Note: 00 and 01 are the only valid settings for these bits.

21:17

Reserved: Set to 0.

Codec Command Valid: Is the command in bits [15:0] valid? 0 = No; 1 = Yes.

This bit is set by hardware when a command is loaded. It remains set until the command has been sent to the codec.

15:0

Codec Command: This is the command being sent to the codec in bits [19:12] of slot 2 on SDATA_OUT.

Offset 10h-11h

Second Level Audio SMI Status Register (RC)

Reset Value = 0000h

15:8

Reserved: Set to 0.

Audio Bus Master 5 SMI Status (Read to Clear): SMI was caused by an event occurring on Audio Bus Master 5?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then

generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1).

CS5530A Datasheet(PDF) 189 Page - Advanced Micro Devices

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