CS5530A datasheet(191/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

191

Revision 1.1

Audio Bus Master 2 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 2?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR+Memory Offset 30h[0] = 1). An SMI is then

generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 31h[0] = 1).

Audio Bus Master 1 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 1?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR+Memory Offset 28h[0] = 1). An SMI is then

generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 29h[0] = 1).

Audio Bus Master 0 SMI Status (Read Only): SMI was caused by an event occurring on Audio Bus Master 0?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR+Memory Offset 20h[0] = 1). An SMI is then

generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 21h[0] = 1).

Codec Serial or GPIO Interrupt SMI Status (Read Only): SMI was caused by a serial or GPIO interrupt from codec?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation enabling for codec serial interrupt: F3BAR+Memory Offset 08h[23] = 1.

SMI generation enabling for codec GPIO interrupt: F3BAR+Memory Offset 00h[30] = 1.

I/O Trap SMI Status (Read Only): SMI was caused by an I/O trap? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory

Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1].

Note: Reading this register does not clear the status bits. See F3BAR+Memory Offset 10h.

Offset 14h-17h

I/O Trap SMI and Fast Write Status Register (RO/RC)

Reset Value = 00000000h

31:24

Fast Path Write Even Access Data (Read Only): These bits contain the data from the last Fast Path Write Even access.

These bits change only on a fast write to an even address.

23:16

Fast Path Write Odd Access Data (Read Only): These bits contain the data from the last Fast Path Write Odd access.

These bits change on a fast write to an odd address, and also on any non-fast write.

Fast Write A1 (Read Only): This bit contains the A1 value for the last Fast Write access.

Read or Write I/O Access (Read Only): Last trapped I/O access was a read or a write? 0 = Read; 1 = Write.

Sound Card or FM Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the sound card or FM I/

O Trap? 0 = No; 1 = Yes. (Note)

Fast Path Write must be enabled, F3BAR+Memory Offset 18h[11] = 1, for the SMI to be reported here. If Fast Path Write is

disabled, the SMI is reported in bit 10 of this register.

This is the third level of SMI status reporting.

The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0].

The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation enabling is at F3BAR+Memory Offset 18h[2].

DMA Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the DMA I/O Trap?

0 = No; 1 = Yes. (Note)

This is the third level of SMI status reporting.

The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0].

The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation enabling is at F3BAR+Memory Offset 18h[8:7].

MPU Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the MPU I/O Trap?

0 = No; 1 = Yes. (Note)

This is the third level of SMI status reporting.

The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0].

The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation enabling is at F3BAR+Memory Offset 18h[6:5].

Table 5-21. F3BAR+Memory Offset xxh: XpressAUDIO™ Subsystem Configuration Registers (Contin-

Bit

Description

CS5530A Datasheet(PDF) 191 Page - Advanced Micro Devices

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