CS5530A datasheet(205/259 Pages) AMD

205 / 259 page

AMD Geode™ CS5530A Companion Device Data Book

205

Revision 1.1

5.4

USB Registers

The USB Host Controller exists logically as its own PCI

“Device”, separate from the Chipset functions. It is a single-

function device, and so it contains a PCI Configuration

space for only Function 0. Depending on the state of the

HOLD_REQ# pin on reset, the USB Controller will respond

to one of two Device numbers for access to its PCI Config-

uration registers:

HOLD_REQ# low:

Responds to pin AD29 high

(Device 13h in a Geode system).

HOLD_REQ# high: Responds to pin AD27 high

(Device 11h in a Geode system).

The PCI Configuration registers are listed in Table 5-25.

They can be accessed as any number of bytes within a sin-

gle 32-bit aligned unit. They are selected by the PCI-stan-

dard Index and Byte-Enable method. Registers marked as

“Reserved”, and reserved bits within a register, should not

be changed by software.

In the PCI Configuration space, there is one Base Address

USB Host Controller's operational register set into a 4K

memory space. Once the BAR register has been initialized,

and the PCI Command register at Index 04h has been set

to enable the Memory space decoder, these “USB Control-

ler” registers are accessible.

The memory-mapped USB Controller Registers are listed

in Table 5-26. They follow the Open Host Controller Inter-

face (OHCI) specification.

Table 5-25. USB Index xxh: USB PCI Configuration Registers

Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 0E11h

Index 02h-03h

Device Identification Register (RO)

Reset Value = A0F8h

Index 04h-05h

Command Register (R/W)

Reset Value = 0000h

15:10

Reserved: Set to 0.

Fast Back-to-Back Enable (Read Only): USB only acts as a master to a single device, so this functionality is not needed.

It is always disabled (must always be set to 0).

SERR#: USB asserts SERR# when it detects an address parity error. 0 = Disable; 1 = Enable.

Wait Cycle Control: USB does not need to insert a wait state between the address and data on the AD lines. It is always

disabled (bit is set to 0).

Parity Error: USB asserts PERR# when it is the agent receiving data and it detects a data parity error.

0 = Disable; 1 = Enable.

VGA Palette Snoop Enable (Read Only): USB does not support this function. It is always disabled (bit is set to 0).

Memory Write and Invalidate: Allow USB to run Memory Write and Invalidate commands. 0 = Disable; 1 = Enable.

The Memory Write and Invalidate command will only occur if the cache line size is set to 32 bytes and the memory write is

exactly one cache line.

If the CS5530A is being used in a GX1 processor based system, this bit must be set to 0.

Special Cycles: USB does not run special cycles on PCI. It is always disabled (bit is set to 0).

PCI Master Enable: Allow USB to run PCI master cycles. 0 = Disable; 1 = Enable.

Memory Space: Allow USB to respond as a target to memory cycles. 0 = Disable; 1 = Enable.

I/O Space: Allow USB to respond as a target to I/O cycles. 0 = Disable; 1 = Enable.

Index 06h-07h

Status Register (R/W)

Reset Value = 0280h

Detected Parity Error: This bit is set whenever the USB detects a parity error, even if the Parity Error (response) detection

enable bit (PCIUSB 04h[6]) is disabled. Write 1 to clear.

SERR# Status: This bit is set whenever the USB detects a PCI address error. Write 1 to clear.

Received Master Abort Status: This bit is set when the USB, acting as a PCI master, aborts a PCI bus memory cycle.

Write 1 to clear.

Received Target Abort Status: This bit is set when a USB generated PCI cycle (USB is the PCI master) is aborted by a

PCI target. Write 1 to clear.

Signaled Target Abort Status: This bit is set whenever the USB signals a target abort. Write 1 to clear.

10:9

DEVSEL# Timing (Read Only): These bits indicate the DEVSEL# timing when performing a positive decode. Since

DEVSEL# is asserted to meet the medium timing, these bits are encoded as 01b.

Data Parity Reported: Set to 1 if the Parity Error Response bit (Command Register bit 6) is set, and USB detects PERR#

asserted while acting as PCI master (whether PERR# was driven by USB or not).

CS5530A Datasheet(PDF) 205 Page - Advanced Micro Devices

CS5530A Datasheet(HTML) 205 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL