CS5530A datasheet(206/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Revision 1.1

Fast Back-to-Back Capable (Read Only): USB does support fast back-to-back transactions when the transactions are not

to the same agent. This bit is always 1.

6:0

Reserved: Set to 0.

Note: The PCI specification defines this register to record status information for PCI related events. This is a read/write register. How-

ever, writes can only reset bits. A bit is reset whenever the register is written and the data in the corresponding bit location is a 1.

Index 08h

Device Revision ID Register (RO)

Reset Value = 06h

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 0C0310h

This register identifies this function as an OpenHCI device. The base class is 0Ch (serial bus controller). The sub class is 03h (universal

serial bus). The programming interface is 10h (OpenHCI).

Index 0Ch

Cache Line Size Register (R/W)

Reset Value = 00h

This register identifies the system cache line size in units of 32-bit WORDs. The USB only stores the value of bit 3 in this register since

the cache line size of 32 bytes is the only value applicable to the design. Any value other than 08h written to this register is read back as

00h.

In a CS5530A/GX1 processor based system this register must be set to 00h since the GX1 processor has a 16-byte cache line size.

Index 0Dh

Latency Timer Register (R/W)

Reset Value = 00h

This register identifies the value of the latency timer in PCI clocks for PCI bus master cycles.

Index 0Eh

Header Type Register (RO)

Reset Value = 00h

This register identifies the type of the predefined header in the configuration space. Since the USB is a single function device and not a

PCI-to-PCI bridge, this byte should be read as 00h.

Index 0Fh

BIST Register (RO)

Reset Value = 00h

This register identifies the control and status of Built In Self Test. The USB does not implement BIST, so this register is read only.

Index 10h-13h

Base Address Register (R/W)

Reset Value = 00000000h

This BAR sets the base address of the memory mapped USB controller registers. Bits [11:0] are read only (0000 0000 0000),

indicating a 4 KB memory address range. Refer to Table 5-26 for the USB controller register bit formats and reset values.

31:12

USB Controller Base Address

11:0

Address Range (Read Only)

Index 14h-3Bh

Reserved

Reset Value = xxh

Index 3Ch

Interrupt Line Register (R/W)

Reset Value = 00h

This register identifies which of the system interrupt controllers the devices interrupt pin is connected to. The value of this register is

used by device drivers and has no direct meaning to the USB.

Index 3Dh

Interrupt Pin Register (RO)

Reset Value = 01h

This register identifies which interrupt pin a device uses. Since the USB uses INTA#, this value is set to 01h.

Index 3Eh

Min. Grant Register (RO)

Reset Value = 00h

This register specifies the desired settings for how long of a burst the USB needs assuming a clock rate of 33 MHz. The value specifies

a period of time in units of 1/4 microsecond.

Index 3Fh

Max. Latency Register (RO)

Reset Value = 50h

This register specifies the desired settings for how often the USB needs access to the PCI bus assuming a clock rate of 33 MHz. The

value specifies a period of time in units of 1/4 microsecond.

Index 40h-43h

ASIC Test Mode Enable Register (R/W)

Reset Value = 000F0000h

Used for internal debug and test purposes only.

Index 44h-45h

ASIC Operational Mode Enable Register (R/W)

Reset Value = 0000h

15:9

Reserved: Read/Write 0s.

SIE Pipeline Disable: When set, waits for all USB bus activity to complete prior to returning completion status to the List

Processor. This is a fail-safe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12

MHz.

7:1

Write Only: Read as 0s.

Data Buffer Region 16: When set, the size of the region for the data buffer is 16 bytes. Otherwise, the size is 32 bytes.

Table 5-25. USB Index xxh: USB PCI Configuration Registers (Continued)

Bit

Description

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