CS5530A datasheet(217/259 Pages) AMD

217 / 259 page

AMD Geode™ CS5530A Companion Device Data Book

217

Revision 1.1

I/O Port 0D0h (R/W)

Read

DMA Status Register, Channels 7:4

Channel 7 Request: Request pending? 0 = No; 1 = Yes.

Channel 6 Request: Request pending? 0 = No; 1 = Yes.

Channel 5 Request: Request pending? 0 = No; 1 = Yes.

Undefined

Channel 7 Terminal Count: TC reached? 0 = No; 1 = Yes.

Channel 6 Terminal Count: TC reached? 0 = No; 1 = Yes.

Channel 5 Terminal Count: TC reached? 0 = No; 1 = Yes.

Undefined

Write

DMA Command Register, Channels 7:4

DACK Sense: 0 = Active high; 1 = Active low.

DREQ Sense: 0 = Active high; 1 = Active low.

Write Selection: 0 = Late write; 1 = Extended write.

Priority Mode: 0 = Fixed; 1 = Rotating.

Timing Mode: 0 = Normal; 1 = Compressed.

Channels 7 through 4: 0 = Disable; 1 = Enable.

1:0

Reserved: Set to 0.

I/O Port 0D2h (WO)

Software DMA Request Register, Channels 7:4

7:3

Reserved: Set to 0.

Request Type: 0 = Reset; 1 = Set.

1:0

Channel Number Request Select: 00 = Illegal; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7.

Note: Software DMA is not supported

I/O Port 0D4h (R/W)

DMA Channel Mask Register, Channels 7:0

7:3

Reserved: Set to 0.

Channel Mask: 0 = Not masked; 1 = Masked.

1:0

Channel Number Mask Select: 00 = Channel 4; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7.

I/O Port 0D6h (WO)

DMA Channel Mode Register, Channels 7:4

7:6

Transfer Mode: 00 = Demand; 01 = Single; 10 = Block; 11 = Cascade.

Address Direction: 0 = Increment; 1 = Decrement.

Auto-initialize: 0 = Disabled; 1 = Enable.

3:2

Transfer Type: 00 = Verify; 01 = Memory read; 10 = Memory write; 11 = Reserved.

1:0

Channel Number Mode Select: 00 = Channel 4; 01 = Channel 5; 10 = Channel 6; 11 = Channel 7.

Channel 4 must be programmed in cascade mode. This mode is not the default.

I/O Port 0D8h (WO)

DMA Clear Byte Pointer Command, Channels 7:4

I/O Port 0DAh (WO)

DMA Master Clear Command, Channels 7:4

I/O Port 0DCh (WO)

DMA Clear Mask Register Command, Channels 7:4

I/O Port 0DEh (WO)

DMA Write Mask Register Command, Channels 7:4

Table 5-27. DMA Channel Control Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 217 Page - Advanced Micro Devices

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