FS98O21 datasheet(74/136 Pages) FORTUNE

74 / 136 page

FS98O21

Rev. 1.7

74/136

Table 7-6 PT2 register table

Address

Name

Referenced

Section

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on Power on Reset

24h

PT2

PT2 [7:0]

uuuuuuuu

25h

PT2EN

PT2EN [7:0]

00000000

26h

PT2PU

PT2PU [7:0]

00000000

27h

PT2MR

7.2/7.5/8

BZEN

00000000

Read data Operation

Clear the PT2EN[n]

18 register flags. The PT2[n] will be defined as an input port.

Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor.

After the signal input from outside, user could get the data through PT2[n]

Write data Operation

Set the PT2EN[n] register flags. The PT2[n] will be defined as an output port.

Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor.

Set the PT2[n] to output the data. The embedded D Flip Flop will latch the data till PT2[n] is changed.

Notice Operation

Parallel a small resistor (about 10k ohm) between ports and VDD to increase the possible output current

when the PT2PU[n] is set.

18 n means the bits indexes user want to control

FS98O21 Datasheet(PDF) 74 Page - Fortune Semiconductor Corp.

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