FS98O21 datasheet(97/136 Pages) FORTUNE

97 / 136 page

FS98O21

Rev. 1.7

97/136

property

R/W-0

U-0

R/W-0

NETC

SREFO

ADG[1:0]

ADEN

Bit7

Bit0

Bit 7

SREFO

: Internal Reference Voltage enable flag. (Please refer to Section 10.1)

1 = Internal Reference Voltage is enabled. VR1P = 2/5 REFO, VR2P = 1/5 REFO

0 = Internal Reference Voltage is disabled. VR1P and VR2P are floating.

Bit 3-2 ADG[1:0]: Internal ADC input gain. (Please refer to Section 10.1)

11 = Internal ADC input gain is 7/3

10 = Internal ADC input gain is 2

01 = Internal ADC input gain is 1

00 = Internal ADC input gain is 2/3

Bit 1

ADEN

: ADC enable flag. (Please refer to Section 10.1)

1 = ADC is enabled.

0 = ADC is disabled.

Bit 0

: ADC differential input ports short controller. (Please refer to Section 10.1)

1 = ADC differential input ports are short and both connect to INL

25 (SINL output).

0 = ADC differential input ports are NOT short. The 2 ports connect to INH and INL.

property

R = Readable bit

W = Writable bit

U = unimplemented bit

- n = Value at Power On

Reset

‘1’ = Bit is Set

‘0’ = Bit is Cleared

X = Bit is unknown

25 That means the ADC input differential voltage is zero. ADC output should be zero counts. User could

measure ADC offset counts when the AZ register flag is set.

FS98O21 Datasheet(PDF) 97 Page - Fortune Semiconductor Corp.

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