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FS98O21 Datasheet(PDF) 95 Page - Fortune Semiconductor Corp. |
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FS98O21 Datasheet(HTML) 95 Page - Fortune Semiconductor Corp. |
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95 / 136 page ![]() FS98O21 Rev. 1.7 95/136 Register NETA at address 18h property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NETA SINL[1:0] SINH[2:0] SFTA[2:0] Bit7 Bit0 Bit 7-6 SINL[1:0]: ADC negative input port signal multiplexer (Please refer to Section 10.1) 11 = The ADC negative input port is connected to TEMPL. (Please refer to Section 4.6) 10 = The ADC negative input port is connected to AIN3 (PT1[3]). 01 = The ADC negative input port is connected to AIN2 (PT1[2]). 00 = The ADC negative input port is connected to AIN1 (PT1[1]). Bit 5-3 SINH[2:0]: Embedded ADC Low Pass Filter input port signal multiplexer (Please refer to Section 10.1) 111 = The ADC Low Pass Filter input port is connected to AGND. (Please refer to Section 4.4) 110 = The ADC Low Pass Filter input port is connected to AIN4 (PT1[4]). 101 = The ADC Low Pass Filter input port is connected to AIN5 (PT1[5]). 100 = The ADC Low Pass Filter input port is connected to TEMPH. (Please refer to Section 4.6) 011 = The ADC Low Pass Filter input port is connected to VRL (ADC referenced voltage negative input). 010 = The ADC Low Pass Filter input port is connected to VRH (ADC referenced voltage positive input). 001 = The ADC Low Pass Filter input port is connected to OP1P (OPAMP non-inverting input port). 000 = The ADC Low Pass Filter input port is connected to OP1O (OPAMP output port). Bit 2 SFTA [2] : FTIN and FTB connector ( ADC Low Pass Filter enable flag) 1 = FTIN and FTB is short. ADC Low Pass Filter is enabled. 0 = FTIN and FTB is open. ADC Low Pass Filter is disabled. Bit 1-0 SFTA [1:0]: ADC positive input port signal multiplexer (Please refer to Section 10.1) 11 = The ADC positive input port is connected to AIN3 (PT1[3]). 10 = The ADC positive input port is connected to AIN2 (PT1[2]). 01 = The ADC positive input port is connected to FTIN (SINH[2:0] multiplexer output port). 00 = The ADC positive input port is connected to FTB (FTIN output signal after Low Pass filter). property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset ‘1’ = Bit is Set ‘0’ = Bit is Cleared X = Bit is unknown |
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