EN0

vSafe5V (max)

vSafe5V (min)

tSrcFRSwap

EN1

PPHV Path

(old Sink)

Enabled

Disabled

Disabled

Enabled

FRS ILIMIT

Enabled

3.0A ILIMIT

PP5V Path

(new Source)

Enabled

1.5A/3.0A ILIMIT

VBUS

27

TPS66020, TPS66021

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SLVSEW8 – AUGUST 2019

Product Folder Links: TPS66020 TPS66021

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Copyright © 2019, Texas Instruments Incorporated

Figure 18. Fast Role Swap Events - Case 2

8.8 Faults

The TPS6602x includes a fault pin, FLT. The FLT pin is an open-drain output and requires an external pull-up

resistor. If the FLT pin is not required, it may be tied to GND or left floating. The FLT pin will be asserted low only

under certain conditions and not all fault conditions will assert the FLT pin, see Table 3. If the FLT pin is

asserted, it will remain asserted for a minimum of tHOLD_FLT regardless if the fault condition is removed. After

8.8.1 Fault Types

Table 3 summarizes the various fault types available along with when the FLT shall be asserted.

Table 3. Fault Types

Fault Name

Fault

FLT

Description

PP5V_UVLO

PP5V undervoltage Lockout

Low

If PP5V input supply is below the PP5V UVLO threshold, the

PP5V path is disabled automatically if enabled or remains

disabled until the PP5V UVLO threshold is exceeded. If a SRC

state is selected to be entered, the device will remain in the

DISABLED state until the UVLO event is removed. The FLT pin

will not be asserted. If a SRC state has been entered

successfully and a UVLO event occurs, the device will enter the

DISABLED state, and the FLT pin will be asserted.

PP5V_OVP

PP5V overvoltage Protection

Low

If a SRC state is selected to be entered or device currently is in

a SRC state (SRC 1.5 A or SRC 3 A) and the PP5V input

supply rises above the PP5V OVP threshold, the PP5V path is

disabled automatically and the FLT pin will be asserted.

PP5V_ILIMIT

PP5V Current Limit Protection

Low

The PP5V power path has a closed-loop current limit protection.

If the load current exceeds the selected current limit, the control

loop will increase the voltage across the FET to compensate.

Note: FLT will not be asserted unless the current limit event

PP5V_OVT

PP5V overtemperature

Protection

Low

If a SRC state is selected to be entered or device currently is in

a SRC state (SRC 1.5 A or SRC 3 A) and the local temperature

of PP5V power path exceeds TSD_PP5V_R while in current

limit, the PP5V path is disabled automatically and the FLT pin

will remain asserted. PP5V power path will remain disabled until

temperature falls below TSD_PP5V_F.