CS47L24 datasheet(4/256 Pages) CIRRUS

4 / 256 page

CS47L24

Rev 4.1

DSP DEBUG SUPPORT.............................................................................................................................................................................................. 104

DIGITAL AUDIO INTERFACE

.......................................................................................................................105

MASTER AND SLAVE MODE OPERATION ............................................................................................................................................................... 106

AUDIO DATA FORMATS............................................................................................................................................................................................. 106

AIF TIMESLOT CONFIGURATION ............................................................................................................................................................................. 107

TDM OPERATION BETWEEN THREE OR MORE DEVICES .................................................................................................................................... 109

DIGITAL AUDIO INTERFACE CONTROL

.....................................................................................................111

AIF SAMPLE RATE CONTROL................................................................................................................................................................................... 111

AIF MASTER / SLAVE CONTROL .............................................................................................................................................................................. 111

AIF SIGNAL PATH ENABLE........................................................................................................................................................................................ 114

AIF BCLK AND LRCLK CONTROL ............................................................................................................................................................................. 117

AIF DIGITAL AUDIO DATA CONTROL ....................................................................................................................................................................... 121

AIF TDM AND TRI-STATE CONTROL ........................................................................................................................................................................ 124

AIF DIGITAL PULL-UP AND PULL-DOWN ................................................................................................................................................................. 125

OUTPUT SIGNAL PATH

................................................................................................................................128

OUTPUT SIGNAL PATH ENABLE .............................................................................................................................................................................. 129

OUTPUT SIGNAL PATH SAMPLE RATE CONTROL................................................................................................................................................. 130

OUTPUT SIGNAL PATH DIGITAL VOLUME CONTROL............................................................................................................................................ 130

OUTPUT SIGNAL PATH DIGITAL VOLUME LIMIT .................................................................................................................................................... 133

OUTPUT SIGNAL PATH NOISE GATE CONTROL .................................................................................................................................................... 134

OUTPUT SIGNAL PATH AEC LOOPBACK ................................................................................................................................................................ 136

ANALOGUE OUTPUTS ............................................................................................................................................................................................... 137

GENERAL PURPOSE INPUT / OUTPUT

......................................................................................................139

GPIO CONTROL.......................................................................................................................................................................................................... 140

GPIO FUNCTION SELECT.......................................................................................................................................................................................... 142

BUTTON DETECT / WRITE SEQUENCER TRIGGER (GPIO INPUT) ....................................................................................................................... 145

LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT)................................................................................................................................................ 145

INTERRUPT (IRQ) STATUS OUTPUT........................................................................................................................................................................ 146

DSP STATUS FLAG (DSP IRQN) OUTPUT ............................................................................................................................................................... 146

OPCLK AND OPCLK_ASYNC CLOCK OUTPUT ....................................................................................................................................................... 146

FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT ........................................................................................................................................... 148

FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT ............................................................................................................................................. 148

PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT ......................................................................................................................................... 149

HEADPHONE ENABLE STATUS OUTPUT ................................................................................................................................................................ 149

BOOT DONE STATUS OUTPUT................................................................................................................................................................................. 149

ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT ............................................................................................. 150

ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) CONFIGURATION ERROR STATUS OUTPUT........................................................... 150

ISOCHRONOUS SAMPLE RATE CONVERTER (ISRC) CONFIGURATION ERROR STATUS OUTPUT................................................................ 150

OVER-TEMPERATURE, SHORT CIRCUIT PROTECTION, AND SPEAKER SHUTDOWN STATUS OUTPUT....................................................... 150

DYNAMIC RANGE CONTROL (DRC) STATUS OUTPUT .......................................................................................................................................... 151

CONTROL WRITE SEQUENCER STATUS OUTPUT ................................................................................................................................................ 151

CONTROL INTERFACE ERROR STATUS OUTPUT ................................................................................................................................................. 152

SYSTEM CLOCKS ENABLE STATUS OUTPUT ........................................................................................................................................................ 152

CLOCKING ERROR STATUS OUTPUT ..................................................................................................................................................................... 153

INTERRUPTS

................................................................................................................................................154

CLOCKING AND SAMPLE RATES

...............................................................................................................165

SYSTEM CLOCKING................................................................................................................................................................................................... 165

SAMPLE RATE CONTROL ......................................................................................................................................................................................... 165

AUTOMATIC SAMPLE RATE DETECTION ................................................................................................................................................................ 166

SYSCLK AND ASYNCCLK CONTROL ....................................................................................................................................................................... 167

MISCELLANEOUS CLOCK CONTROLS .................................................................................................................................................................... 170

BCLK AND LRCLK CONTROL .................................................................................................................................................................................... 175

CONTROL INTERFACE CLOCKING .......................................................................................................................................................................... 176

FREQUENCY LOCKED LOOP (FLL) .......................................................................................................................................................................... 176

FREE-RUNNING FLL MODE....................................................................................................................................................................................... 186

SPREAD SPECTRUM FLL CONTROL ....................................................................................................................................................................... 188

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