CS47L24 datasheet(71/256 Pages) CIRRUS

71 / 256 page

CS47L24

Rev 4.1

DSPnLMIX_VOL2

DSPnLMIX_VOL3

DSPnLMIX_VOL4

DSPnLMIX_VOL1

DSPnLMIX_SRC1

DSPnLMIX_SRC3

DSPnLMIX_SRC4

DSPnLMIX_SRC2

DSPnRMIX_VOL2

DSPnRMIX_VOL3

DSPnRMIX_VOL4

DSPnRMIX_VOL1

DSPnRMIX_SRC1

DSPnRMIX_SRC3

DSPnRMIX_SRC4

DSPnRMIX_SRC2

DSP n

DSPn Channel 1

DSPn Channel 2

DSPn Channel 3

DSPn Channel 4

DSPn Channel 5

DSPn Channel 6

CS47L24 supports 2 DSP blocks, ie. n = 2 or 3. Note that DSP1 is not implemented on this device.

DSP2 Outputs:

(70h, 71h, 72h,

73h, 74h, 75h)

DSP3 Outputs:

(78h, 79h, 7Ah,

7Bh, 7Ch, 7Dh)

Figure 21 Digital Core DSP Blocks

The DSP2 and DSP3 mixer / input control registers (see Figure 21) are located at register addresses R2432 (980h)

through to R2552 (9F8h). (Note that DSP1 is not implemented on this device.)

The full list of digital mixer control registers is provided in th

e “Register Map” section (Register R1600 through to R3000).

Generic register definitions are provided in Table 7.

The *_SRCn registers select the input source(s) for the respective DSP processing blocks. Note that the selected input

source(s) must be configured for the same sample rate as the DSP to which they are connected. Sample rate conversion

functions are available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and

“Isochronous Sample Rate Converter (ISRC)”.

The bracketed numbers in Figure 21,

e.g.,”(68h)” indicate the corresponding *_SRCn register setting for selection of that

signal as an input to another digital core function.

The sample rate for each of the DSP functions is configured using the respective DSPn_RATE registers - see Table 21.

Sample rate conversion is required when routing the DSPn signal paths to any signal chain that is asynchronous and/or

configured for a different sample rate.

The CS47L24 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the

commanded DSP mixing functions. If an attempt is made to enable a DSP mixer path, and there are insufficient SYSCLK

cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be

affected under these circumstances.)

The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See “General Purpose

Input / Output

” and “Interrupts” for further details.

The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error

condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled.

The CS47L24 supports up to eight DSP Status flags as outputs from the DSP blocks. These are configurable within the

DSP to provide external indication of the required function(s). The DSP Status flags can be read using the

DSP_IRQn_STS registers described in Table 66

(see “Interrupts”).

The DSP Status flags are inputs to the Interrupt control circuit and can be used to trigger an interrupt event - see

“Interrupts”.

The DSP Status flags can be output directly on a GPIO pin as an external indication of the DSP Status. S

ee “General

Purpose Input / Output

” to configure a GPIO pin for this function.

CS47L24 Datasheet(PDF) 71 Page - Cirrus Logic

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