CS47L24 datasheet(78/256 Pages) CIRRUS

78 / 256 page

CS47L24

Rev 4.1

PWM GENERATOR

The CS47L24 incorporates two Pulse Width Modulation (PWM) signal generators as illustrated in Figure 25. The duty

cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register

setting.

A 4-input mixer is associated with each PWM generator. The 4 input sources are selectable in each case, and

independent volume control is provided for each path.

The PWM signal generators can

be output directly on a GPIO pin. See “General Purpose Input / Output” to configure a

GPIO pin for this function.

Note that the PWM output should always be disabled whenever the system clock, SYSCLK, is disabled. Failure to do this

may result in a persistent lo

gic ‘1’ DC output from the PWM generator. See “Clocking and Sample Rates” for details of

system clocking and the associated control requirements.

Note that the PWM signal generators cannot be selected as input to the digital mixers or signal processing functions

within the CS47L24 digital core.

PWM1MIX_VOL2

PWM1MIX_VOL3

PWM1MIX_VOL4

PWM1MIX_VOL1

PWM1MIX_SRC1

PWM1MIX_SRC3

PWM1MIX_SRC4

PWM1MIX_SRC2

GPIO

(GPn = 08h)

PWM1

PWM1_ENA

PWM1_OVD

PWM1_LVL

PWM2MIX_VOL2

PWM2MIX_VOL3

PWM2MIX_VOL4

PWM2MIX_VOL1

PWM2MIX_SRC1

PWM2MIX_SRC3

PWM2MIX_SRC4

PWM2MIX_SRC2

GPIO

(GPn = 09h)

PWM2

PWM2_ENA

PWM2_OVD

PWM2_LVL

PWM_RATE

PWM_CLK_SEL

When PWMn_OVD = 0, the PWM duty cycle is controlled by the respective digital audio mixer.

When PWMn_OVD = 1, the PWM duty cycle is set by PWMn_LVL.

The PWM sample rate and clocking frequency are selected using PWM_RATE and PWM_CLK_SEL.

Figure 25 Digital Core Pulse Width Modulation (PWM) Generator

The PWM1 and PWM2 mixer control registers (see Figure 25) are located at register addresses R1600 (640h) through to

R1615 (64Fh).

The full list of digital mixer control regis

ters is provided in the “Register Map” section (Register R1600 through to R3000).

Generic register definitions are provided in Table 7.

The *_SRCn registers select the input source(s) for the respective mixers. Note that the selected input source(s) must be

configured for the same sample rate as the mixer to which they are connected. Sample rate conversion functions are

available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous

Sample Rate Converter (ISRC)

”.

CS47L24 Datasheet(PDF) 78 Page - Cirrus Logic

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