CS47L24 datasheet(85/256 Pages) CIRRUS

85 / 256 page

CS47L24

Rev 4.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3584

(0E00h)

FX_Ctrl

14:11

FX_RATE [3:0]

0000

FX Sample Rate (EQ, LHPF, DRC)

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

1000 = ASYNC_SAMPLE_RATE_1

1001 = ASYNC_SAMPLE_RATE_2

All other codes are Reserved.

The selected sample rate is valid in the

range 8kHz to 192kHz.

When the DRC is enabled, the maximum

FX_RATE sample rate is 96kHz.

All EQnMIX_SRCm, DRCnxMIX_SRCm,

and LHPFnMIX_SRCm registers should

be set to 00h before changing FX_RATE.

R4608

(1200h)

DSP2

Control 1

14:11

DSP2_RATE

[3:0]

0000

DSP2 Sample Rate

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

1000 = ASYNC_SAMPLE_RATE_1

1001 = ASYNC_SAMPLE_RATE_2

All other codes are Reserved.

The selected sample rate is valid in the

range 4kHz to 192kHz.

All DSP2xMIX_SRCn registers should be

set to 00h before changing DSP2_RATE.

R4864

(1300h)

DSP3

Control 1

14:11

DSP3_RATE

[3:0]

0000

DSP3 Sample Rate

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

1000 = ASYNC_SAMPLE_RATE_1

1001 = ASYNC_SAMPLE_RATE_2

All other codes are Reserved.

The selected sample rate is valid in the

range 4kHz to 192kHz.

All DSP3xMIX_SRCn registers should be

set to 00h before changing DSP3_RATE.

Table 21 Digital Core Sample Rate Control

ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC)

The CS47L24 supports multiple signal paths through the digital core. Two independent clock domains are supported,

referenced to SYSCLK and ASYNCCLK

respectively, as described in “Clocking and Sample Rates”. Every digital signal

path must be synchronised either to SYSCLK or to ASYNCCLK.

The Asynchronous Sample Rate Converter (ASRC) provides two stereo signal paths between the SYSCLK and

ASYNCCLK domains, as illustrated in Figure 28.

The sample rate on the SYSCLK domain is selected using the ASRC_RATE1 register - the rate can be set equal to

SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3.

The sample rate on the ASYNCCLK domain is selected using the ASRC_RATE2 register - the rate can be set equal to

ASYNC_SAMPLE_RATE_1 or ASYNC_SAMPLE_RATE_2.

See “Clocking and Sample Rates” for details of the sample rate control registers.

The ASRC_RATE1 and ASRC_RATE2 registers should not be changed if any of the respective *_SRCn registers is non-

zero. The associated *_SRCn registers should be cleared to 00h before writing new values to ASRC_RATE1 or

ASRC_RATE2. A minimum delay of 125µs should be allowed between clearing the *_SRCn registers and writing to the

associated ASRC_RATE1 or ASRC_RATE2 registers. See Table 22 for further details.

The ASRC supports sample rates in the range 8kHz to 48kHz only. The applicable SAMPLE_RATE_n and

ASYNC_SAMPLE_RATE_n registers must each select sample rates between 8kHz and 48kHz when any ASRC path is

enabled.

CS47L24 Datasheet(PDF) 85 Page - Cirrus Logic

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