CS47L24 datasheet(35/256 Pages) CIRRUS

35 / 256 page

CS47L24

Rev 4.1

Two digital microphone channels are interleaved on DMICDATn. The digital microphone interface timing is illustrated in

Figure 11. Each microphone must tri-state its data output when the other microphone is transmitting.

DMICCLKn pin

DMICDATn pin

(Left & Right

channels interleaved)

Left Mic output

Right Mic output

hi-Z

Figure 11 Digital Microphone Interface Timing

When digital microphone input is enabled, the CS47L24 outputs a clock signal on the applicable DMICCLK pin(s). The

DMICCLK frequency is selectable, as described in Table 1.

Note that SYSCLK must be present and enabled when using the Digital

Microphone inputs; see “Clocking and Sample

Rates

” for details of SYSCLK and the associated register control fields.

INPUT SIGNAL PATH ENABLE

The input signal paths are enabled using the register bits described in Table 2. The respective bit(s) must be enabled for

digital input on the respective input path(s).

The input signal paths are muted by default. It is recommended that de-selecting the mute should be the final step of the

path enable control sequence. Similarly, the mute should be selected as the first step of the path disable control

sequence. The input signal path mute functions are controlled using the register bits described in Table 4.

The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The ASYNCCLK clock

may also be required, depending on the path configuration. See “Clocking and Sample Rates” for details of the system

clocks.

The CS47L24 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the input

signal paths. If an attempt is made to enable an input signal path, and there are insufficient SYSCLK cycles to support it,

then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these

circumstances.)

The Underclocked Error condition can be monitored using the GPIO and/

or Interrupt functions. See “General Purpose

Input / Output

” and “Interrupts” for further details.

The status bits in Register R769 indicate the status of each of the input signal paths. If an Underclocked Error condition

occurs, then these bits provide readback of which input signal path(s) have been successfully enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R768

(0300h)

Input

Enables

IN2L_ENA

Input Path 2 (Left) Enable

0 = Disabled

1 = Enabled

IN2R_ENA

Input Path 2 (Right) Enable

0 = Disabled

1 = Enabled

IN1L_ENA

Input Path 1 (Left) Enable

0 = Disabled

1 = Enabled

CS47L24 Datasheet(PDF) 35 Page - Cirrus Logic

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