CS47L24 datasheet(72/256 Pages) CIRRUS

72 / 256 page

CS47L24

Rev 4.1

The DSP_IRQn_STS fields are read-only bits. These bits can be set (or reset) by writing to the DSP_IRQn fields, as

described in Table 16. This facility can be used to allow a DSP core to generate an interrupt to the host processor. The

DSP interrupt registers are asserted on the rising and falling edges of the respective DSP_IRQn fields.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3393

(0D41h)

ADSP2

IRQ0

DSP_IRQ2

DSP IRQ2

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ2_EINTn

interrupt to the host processor.

DSP_IRQ1

DSP IRQ1

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ1_EINTn

interrupt to the host processor.

R3394

(0D42h)

ADSP2

IRQ1

DSP_IRQ4

DSP IRQ4

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ4_EINTn

interrupt to the host processor.

DSP_IRQ3

DSP IRQ3

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ3_EINTn

interrupt to the host processor.

R3395

(0D43h)

ADSP2

IRQ2

DSP_IRQ6

DSP IRQ6

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ6_EINTn

interrupt to the host processor.

DSP_IRQ5

DSP IRQ5

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ5_EINTn

interrupt to the host processor.

R3396

(0D44h)

ADSP2

IRQ3

DSP_IRQ8

DSP IRQ8

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ8_EINTn

interrupt to the host processor.

DSP_IRQ7

DSP IRQ7

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ7_EINTn

interrupt to the host processor.

Table 16 DSP Interrupts

CS47L24 Datasheet(PDF) 72 Page - Cirrus Logic

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