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CS47L24 Datasheet(PDF) 18 Page - Cirrus Logic

Part # CS47L24
Description  Low Power Audio Hub for Wearable Technology
PDF  256 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L24 Datasheet(HTML) 18 Page - Cirrus Logic

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CS47L24
18
Rev 4.1
Test Conditions
DBVDD = CPVDD = AVDD = 1.8V, MICVDD = 2.2V, DCVDD = 1.2V, SPKVDD = 4.2V,
TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Bias (MICBIAS1, MICBIAS2)
Note - No capacitor on MICBIASn
Note - In regulator mode, it is required that VMICVDD - VMICBIAS > 200mV
Minimum Bias Voltage
VMICBIAS
Regulator mode
(MICBn_BYPASS=0)
Load current
≤ 1.0mA
1.5
V
Maximum Bias Voltage
2.8
V
Bias Voltage output step size
0.1
V
Bias Voltage accuracy
-5%
+5%
V
Bias Current
Regulator mode
(MICBn_BYPASS=0),
VMICVDD - VMICBIAS >200mV
2.4
mA
Bypass mode
(MICBn_BYPASS=1)
5.0
Output Noise Density
Regulator mode
(MICBn_BYPASS=0),
MICBn_LVL = 4h,
Load current = 1mA,
Measured at 1kHz
40
nV/
Hz
Integrated noise voltage
Regulator mode
(MICBn_BYPASS=0),
MICBn_LVL = 4h,
Load current = 1mA,
100Hz to 7kHz, A-weighted
2.5
µVrms
Power Supply Rejection Ratio
(DBVDD, CPVDD, AVDD)
PSRR
100mV (peak-peak) 217Hz
100
dB
100mV (peak-peak) 10kHz
80
Power Supply Rejection Ratio
(MICVDD)
PSRR
100mV (peak-peak) 217Hz
82
dB
100mV (peak-peak) 10kHz
44
Power Supply Rejection Ratio
(DCVDD)
PSRR
100mV (peak-peak) 217Hz
102
dB
100mV (peak-peak) 10kHz
94
Power Supply Rejection Ratio
(SPKVDD)
PSRR
100mV (peak-peak) 217Hz
99
dB
100mV (peak-peak) 10kHz
92
Load capacitance
Regulator mode
(MICBn_BYPASS=0),
MICBn_EXT_CAP=0
50
pF
Regulator mode
(MICBn_BYPASS=0),
MICBn_EXT_CAP=1
1.8
4.7
µF
Output discharge resistance
MICBn_ENA=0,
MICBn_DISCH=1
2
kΩ
Frequency Locked Loop (FLL1, FLL2)
Output frequency
39
156
MHz
Lock Time
FREF = 32kHz,
FOUT = 147.456MHz
10
ms
FREF = 12MHz,
FOUT = 147.456MHz
1
RESET pin Input
RESET input pulse width
(To trigger a Hardware Reset, the
RESET input must be asserted for
longer than this duration)
1
µs



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