CS47L24 datasheet(28/256 Pages) CIRRUS

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CS47L24

Rev 4.1

CONTROL INTERFACE TIMING

(input)

SCLK

(input)

MOSI

(input)

tSSU

tSCH

tSCL

tSCY

tDHO

tDSU

tSHO

Figure 6 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle)

SCLK

(input)

MISO

(output)

tDL

(input)

Figure 7 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle)

Test Conditions

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

¯¯ falling edge to SCLK rising edge

tSSU

2.6

SCLK falling edge to SS

¯¯ rising edge

tSHO

SCLK pulse cycle time

SYSCLK disabled

(SYSCLK_ENA=0)

tSCY

38.4

SYSCLK_ENA=1 and

SYSCLK_FREQ = 000

76.8

SYSCLK_ENA=1 and

SYSCLK_FREQ > 000

38.4

SCLK pulse width low

tSCL

15.3

SCLK pulse width high

tSCH

15.3

MOSI to SCLK set-up time

tDSU

1.5

MOSI to SCLK hold time

tDHO

1.7

SCLK falling edge to

MISO transition

SCLK slew (90% to 10%) = 5ns,

CLOAD (MISO) = 25pF

tDL

11.9

CS47L24 Datasheet(PDF) 28 Page - Cirrus Logic

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